DLL-conscious instruction fetch optimization for SMT processors

ACKNOWLEDGEMENTS There are many who have given me inspiration, guidance and provided me with professional and personal support. First of all, I would like to extend my heartfelt thanks to my parents for the unwavering support they provided me in every way possible, in order to enable me reach both educational and personal goals. I would also like to thank my brothers, for always being there whenever I needed their support. My family has been a critical part of my educational endeavors and their efforts will always be appreciated and remembered. I would like to extend my appreciation to my advisor Dr. Hsien-Hsin Sean Lee for his strong support throughout the time I have worked with him and for helping me understand that there is always room for realizing higher potential in myself. My sincere thanks also goes to Dr. Sung Kyu Lim and Dr. Sudhakar Yalamanchili for serving on my thesis committee. In addition, I would also like to thank Mrinmoy Ghosh for providing me with valuable advice and suggestions to improve my work. I would also like to thank everyone in the MARS (Microprocessor Architecture Research Society) group who have provided a stimulating environment to learn many things and foster new ideas. Last but not the least, I would like to extend my gratitude to many friends in my classes and outside, who have all influenced me in a constructive manner. SUMMARY Simultaneous multithreading (SMT) processors can issue multiple instructions from distinct processes or threads in the same cycle. This technique effectively increases the overall throughput by keeping the pipeline resources more occupied at the potential expense of reducing single thread performance due to resource sharing. In the software domain, an increasing number of Dynamically Linked Libraries (DLL) are used by applications and operating systems, providing better flexibility and modularity, and enabling code sharing. It is observed that a significant amount of execution time in software today is spent in executing standard DLL instructions, that are shared among multiple threads or processes. However, for an SMT processor with a virtually-indexed based cache implementation, existing instruction fetching mechanisms can induce unnecessary false cache misses caused by the DLL-based instructions, which were intended to be shared. This problem is more conspicuous when multiple independent threads are executing concurrently inside an SMT processor. This work investigates an often-neglected form of contention between running threads in the I-TLB and I-cache caused by …